PLA Minimization for Low Power VLSI Designs

In this paper we study the problem of optimizing the two-level representation of a Boolean function in order to minimize power consumption in PLAs. We first give power models used to estimate the power consumption in pseudo-NMOS and dynamic PLAs. Using these power cost functions we then prove that a minimum power solution for dynamic PLAs consists only of prime implicants of the function. For pseudo-NMOS PLAs we show that for incompletely specified multiple output functions, the minimal solution may contain non-prime implicants. We then describe exact and heuristic solutions for minimizing the power consumption of a Boolean function implemented using PLAs. We finally use the results of our experiments to draw conclusions on the effectiveness of low power two-level function minimization for PLAs.